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RTAS
1997
IEEE
15 years 10 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
VISUALIZATION
1997
IEEE
15 years 10 months ago
Multiresolution compression and reconstruction
This paper presents a framework for multiresolution compression and geometric reconstruction of arbitrarily dimensioned data designed for distributed applications. Although being ...
Oliver G. Staadt, Markus H. Gross, Roger Weber
DAC
1997
ACM
15 years 10 months ago
COSYN: Hardware-Software Co-Synthesis of Embedded Systems
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...
Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. J...
DAC
1997
ACM
15 years 10 months ago
More Practical Bounded-Skew Clock Routing
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
Andrew B. Kahng, Chung-Wen Albert Tsao
PLDI
1997
ACM
15 years 10 months ago
Flick: A Flexible, Optimizing IDL Compiler
An interface definition language (IDL) is a nontraditional language for describing interfaces between software components. IDL compilers generate “stubs” that provide separat...
Eric Eide, Kevin Frei, Bryan Ford, Jay Lepreau, Ga...
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