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ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
15 years 10 months ago
Minimum area retiming with equivalent initial states
Traditional minimum area retiming algorithms attempt to achieve their prescribed objective with no regard to maintaining the initial state of the system. This issue is important f...
Naresh Maheshwari, Sachin S. Sapatnekar
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
15 years 10 months ago
PRIMA: passive reduced-order interconnect macromodeling algorithm
— This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel ...
Altan Odabasioglu, Mustafa Celik, Lawrence T. Pile...
RTSS
1997
IEEE
15 years 10 months ago
On-the-fly symbolic model checking for real-time systems
This paper presents an on-the-fly and symbolic algorithm for checking whether a timed automaton satisfies a formula of a timed temporal logic which is more expressive than TCTL....
Ahmed Bouajjani, Stavros Tripakis, Sergio Yovine
PLDI
1997
ACM
15 years 10 months ago
Data-centric Multi-level Blocking
We present a simple and novel framework for generating blocked codes for high-performance machines with a memory hierarchy. Unlike traditional compiler techniques like tiling, whi...
Induprakas Kodukula, Nawaaz Ahmed, Keshav Pingali
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 10 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi