117 search results - page 13 / 24 » NOC architecture design for multi-cluster chips |
153
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CODES
2008
IEEE
16 years 15 days ago
2008
IEEE
As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-onChip (...
164
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DSN
2006
IEEE
16 years 2 days ago
2006
IEEE
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
182
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RTCSA
2008
IEEE
16 years 12 days ago
2008
IEEE
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
159
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IESS
2007
Springer
16 years 5 days ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
180
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NOCS
2009
IEEE
16 years 22 days ago
2009
IEEE
With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distrib...