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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
15 years 6 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
PARELEC
2006
IEEE
16 years 27 days ago
Building Mini-Grid Environments with Virtual Private Networks: A Pragmatic Approach
At our university, we have a number of small-tomedium-size compute clusters and some technical simulations which could benefit from using several of these clusters simulaneously....
Christian Kauhaus, Dietmar Fey
ICPADS
2002
IEEE
15 years 11 months ago
Adaptive Matrix Multiplication in Heterogeneous Environments
In this paper, an adaptive matrix multiplication algorithm for dynamic heterogeneous environments is developed and evaluated. Unlike the state-of-the-art approaches, where load ba...
Bo Hong, Viktor K. Prasanna
VLSISP
2010
119views more  VLSISP 2010»
15 years 1 months ago
Hardware Acceleration of HMMER on FPGAs
We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for bio...
Steven Derrien, Patrice Quinton
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
15 years 4 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt