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IPPS
2005
IEEE
16 years 6 days ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
DAC
2002
ACM
16 years 7 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
FGCS
2006
74views more  FGCS 2006»
15 years 6 months ago
A performance model of non-deterministic particle transport on large-scale systems
In this work we present a predictive analytical model that encompasses the performance and scaling characteristics of a nondeterministic particle transport application, MCNP (Mont...
Mark M. Mathis, Darren J. Kerbyson, Adolfy Hoisie
CCGRID
2006
IEEE
15 years 8 months ago
Integrating Logical and Physical File Models in the MPI-IO Implementation for "Clusterfile"
This paper presents the design and implementation of the MPI-IO interface for the Clusterfile parallel file system. The approach offers the opportunity of achieving a high corelat...
Florin Isaila, David E. Singh, Jesús Carret...
IPPS
2010
IEEE
15 years 4 months ago
Oversubscription on multicore processors
Abstract: Existing multicore systems already provide deep levels of thread parallelism. Hybrid programming models and composability of parallel libraries are very active areas of r...
Costin Iancu, Steven Hofmeyr, Filip Blagojevic, Yi...