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» Multiple Faults: Modeling, Simulation and Test
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ARVLSI
1995
IEEE
146views VLSI» more  ARVLSI 1995»
15 years 9 months ago
Array-of-arrays architecture for parallel floating point multiplication
This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
H. Dhanesha, K. Falakshahi, Mark Horowitz
IWCMC
2006
ACM
15 years 12 months ago
Radio propagation patterns in wireless sensor networks: new experimental results
Wireless sensors use low power radio transceivers due to the stringent constraints on battery capacity. As a result, radio transmission with wireless sensors is unreliable. Furthe...
Tereus Scott, Kui Wu, Daniel Hoffman
GECCO
2004
Springer
145views Optimization» more  GECCO 2004»
15 years 11 months ago
Search Based Automatic Test-Data Generation at an Architectural Level
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Yuan Zhan, John A. Clark
DFT
2005
IEEE
81views VLSI» more  DFT 2005»
15 years 11 months ago
Modeling QCA Defects at Molecular-level in Combinational Circuits
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
TSE
2010
197views more  TSE 2010»
15 years 17 days ago
A Genetic Algorithm-Based Stress Test Requirements Generator Tool and Its Empirical Evaluation
Genetic algorithms (GAs) have been applied previously to UML-driven, stress test requirements generation with the aim of increasing chances of discovering faults relating to networ...
Vahid Garousi