395 search results - page 36 / 79 » Multilevel Circuit Partitioning |
162
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ISPD
2000
ACM
15 years 10 months ago
2000
ACM
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
142
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
146
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
159
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TCAD
1998
15 years 5 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
152
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COMPGEOM
2010
ACM
15 years 11 months ago
2010
ACM
We revisit one of the most fundamental classes of data structure problems in computational geometry: range searching. Back in SoCG’92, Matouˇsek gave a partition tree method fo...