395 search results - page 21 / 79 » Multilevel Circuit Partitioning |
183
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ASPDAC
2006
ACM
15 years 12 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
159
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GECCO
2004
Springer
15 years 11 months ago
2004
Springer
We propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic whic...
133
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ASPDAC
2000
ACM
15 years 9 months ago
2000
ACM
We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to re...
