Sciweavers

395 search results - page 20 / 79
» Multilevel Circuit Partitioning
Sort
View
DAC
1999
ACM
15 years 10 months ago
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
Mauro Chinosi, Roberto Zafalon, Carlo Guardiani
ATS
1998
IEEE
76views Hardware» more  ATS 1998»
15 years 10 months ago
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
Michael S. Hsiao, Srimat T. Chakradhar
DAC
1996
ACM
15 years 10 months ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
DAC
1994
ACM
15 years 10 months ago
Partitioning Very Large Circuits Using Analytical Placement Techniques
A new partitioningapproach for very largecircuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that pro ts from a linear objecti...
Bernhard M. Riess, Konrad Doll, Frank M. Johannes
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
15 years 10 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee