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» Multi-torrent: a performance study and applications
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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 28 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
GLVLSI
2007
IEEE
211views VLSI» more  GLVLSI 2007»
16 years 26 days ago
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
Salvatore Carta, Andrea Acquaviva, Pablo Garcia De...
IEEEPACT
2006
IEEE
16 years 17 days ago
Hardware support for spin management in overcommitted virtual machines
Multiprocessor operating systems (OSs) pose several unique and conflicting challenges to System Virtual Machines (System VMs). For example, most existing system VMs resort to gan...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ETRA
2006
ACM
101views Biometrics» more  ETRA 2006»
16 years 15 days ago
Gaze-contingent temporal filtering of video
We describe an algorithm for manipulating the temporal resolution of a video in real time, contingent upon the viewer’s direction of gaze. The purpose of this work is to study t...
Martin Böhme, Michael Dorr, Thomas Martinetz,...
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
16 years 14 days ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl