This paper examines the suitability and use of runtime verification as means for monitoring security protocols and their properties. In particular, we employ the runtime verificat...
The advent of nanometer feature sizes in silicon fabrication has triggered a number of new design challenges for computer designers. These challenges include design complexity and...
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
The continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. Some researchers have already built simple computation engines by manipulatin...
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...