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ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 11 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
LCN
1998
IEEE
15 years 11 months ago
Providing Rate Guarantees to TCP over the ATM GFR Service
The ATM Guaranteed Frame Rate GFR service is intended for best e ort tra c that can bene t from minimum throughput guarantees. Edge devices connecting LANs to an ATM network can u...
Rohit Goyal, Raj Jain, Sonia Fahmy, Bobby Vandalor...
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
15 years 11 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
RSP
1998
IEEE
110views Control Systems» more  RSP 1998»
15 years 11 months ago
Rapid Design of Discrete Orthonormal Wavelet Transforms
A rapid design methodology for orthonormal wavelet transform cores has been developed. This methodology is based on a generic, scaleable architecture utilising time-interleaved co...
Shahid Masud, John V. McCanny
RTAS
1998
IEEE
15 years 11 months ago
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
In the past, environmental restrictions on size, weight, and power consumption have severely limited both the processing and storage capacity of embedded signal processing systems...
Steve Goddard, Kevin Jeffay
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