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ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
16 years 3 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
16 years 3 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
SOFSEM
2010
Springer
16 years 3 months ago
Regret Minimization and Job Scheduling
Regret minimization has proven to be a very powerful tool in both computational learning theory and online algorithms. Regret minimization algorithms can guarantee, for a single de...
Yishay Mansour
CSCW
2010
ACM
16 years 3 months ago
Are you having difficulty?
It would be useful if software engineers/instructors could be aware that remote team members/students are having difficulty with their programming tasks. We have developed an appr...
Jason Carter, Prasun Dewan
CVPR
2010
IEEE
16 years 3 months ago
Optimizing One-Shot Recognition with Micro-Set Learning
For object category recognition to scale beyond a small number of classes, it is important that algorithms be able to learn from a small amount of labeled data per additional clas...
Kevin Tang, Marshall Tappen, Rahul Sukthankar, Chr...
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