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FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 11 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
157
Voted
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 11 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
ICCAD
1993
IEEE
111views Hardware» more  ICCAD 1993»
15 years 11 months ago
Unifying synchronous/asynchronous state machine synthesis
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
Kenneth Y. Yun, David L. Dill
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 11 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
APGV
2007
ACM
115views Visualization» more  APGV 2007»
15 years 10 months ago
A roughness measure for 3D mesh visual masking
3D models are subject to a wide variety of processing operations such as compression, simplification or watermarking, which introduce slight geometric modifications on the shape. ...
Guillaume Lavoué
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