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DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
15 years 10 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
APSEC
2001
IEEE
15 years 10 months ago
Expert Maintainers' Strategies and Needs when Understanding Software: A Case Study Approach
Accelerating the learning curve of software maintainers working on systems with which they have little familiarity motivated this study. A working hypothesis was that automated me...
Christos Tjortjis, Paul J. Layzell
ASYNC
2001
IEEE
164views Hardware» more  ASYNC 2001»
15 years 10 months ago
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism
This paper describes the synthesis and hardware implementation of a signal-type asynchronous data communication mechanism (ACM). Such an ACM can be used in systems where a data-dr...
Alexandre Yakovlev, Fei Xia, Delong Shang
CAV
2000
Springer
125views Hardware» more  CAV 2000»
15 years 10 months ago
Efficient Reachability Analysis of Hierarchical Reactive Machines
Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile th...
Rajeev Alur, Radu Grosu, Michael McDougall
ICCAD
1995
IEEE
95views Hardware» more  ICCAD 1995»
15 years 10 months ago
A sequential quadratic programming approach to concurrent gate and wire sizing
With an ever-increasing portion of the delay in highspeed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By t...
Noel Menezes, Ross Baldick, Lawrence T. Pileggi