15635 search results - page 294 / 3127 » Modelling and Design of VAML |
169
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CODES
2009
IEEE
16 years 1 months ago
2009
IEEE
This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach n...
198
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
155
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
165
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ICASSP
2009
IEEE
16 years 1 months ago
2009
IEEE
This paper describes a method for designing oversampled DFT filter banks (FB) optimized for subband acoustic echo cancellation (AEC). For this application, the design requirements...
170
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KBSE
2009
IEEE
16 years 1 months ago
2009
IEEE
—As software projects continue to grow in scale, being able to maximize the work that developers can carry out in parallel as a set of concurrent development tasks, without incur...