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» Modelling and Design of VAML
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DATE
2002
IEEE
86views Hardware» more  DATE 2002»
15 years 11 months ago
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
By using a macro/micro state model we show how assumptions on the resolution of logical and physical timing of computation in computer systems has resulted in design methodologies...
JoAnn M. Paul, Donald E. Thomas
EUROMICRO
1999
IEEE
15 years 10 months ago
Validation of Object Oriented Models using Animation
Experience has shown that prototypingis a valuabletechnique in the validation of designs. However, the prototype(s) can be too far semantically removed from the design. Animation ...
Ian Oliver, Stuart Kent
WSC
2000
15 years 7 months ago
Toward a standard process: the use of UML for designing simulation models
Designing complex simulation models is a task essentially associated with software engineering. In this paper, the Unified Modeling Language (UML) is used to specify simulation mo...
Hendrik Richter, Lothar März
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
16 years 14 days ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
ERLANG
2003
ACM
15 years 11 months ago
Extending the VoDKA architecture to improve resource modelling
VoDKA is a Video-on-Demand server developed using Erlang/OTP. In this paper, the evolution of the core architecture of the system, designed for improving resource modelling, is de...
Juan José Sánchez Penas, Carlos Abal...