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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
16 years 24 days ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
134
Voted
HCI
2007
15 years 8 months ago
The BIC Model: A Blueprint for the Communicator
In this paper, we outline a cognitive architecture for communicators, called the BIC model. The model consist of three main components. First, a (B)iological component, in which th...
Jan Peter de Ruiter, Nicholas J. Enfield
DAC
2010
ACM
15 years 7 months ago
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression
In this paper, we propose a novel multi-mode/multi-corner sparse regression (MSR) algorithm to build large-scale performance models of integrated circuits at multiple working mode...
Wangyang Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xi...
MODELS
2009
Springer
16 years 1 months ago
Model Based Architecting and Construction of Embedded Systems (ACES-MB 2009)
The second ACES-MB workshop brought together researchers and practitioners interested in model-based software engineering for realtime embedded systems, with a particular focus on ...
Stefan Van Baelen, Thomas Weigert, Ileana Ober, Hu...
KBSE
2006
IEEE
16 years 25 days ago
Modularity Analysis of Logical Design Models
Traditional design representations are inadequate for generalized reasoning about modularity in design and its technical and economic implications. We have developed an architectu...
Yuanfang Cai, Kevin J. Sullivan