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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 1 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
HPDC
2007
IEEE
16 years 1 months ago
An architecture for virtual organization (VO)-based effective peering of content delivery networks
The proprietary nature of existing Content Delivery Networks (CDNs) means they are closed and do not naturally cooperate, resulting in “islands” of CDNs. Finding ways for dist...
Al-Mukaddim Khan Pathan, James Broberg, Kris Buben...
ASPLOS
2006
ACM
16 years 23 days ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
EWSA
2004
Springer
16 years 5 days ago
An Architecture Description Language for Mobile Distributed Systems
Mobile software applications have to meet new requirements directly arising from mobility issues. To address these requirements at an early stage in development, an architecture d...
Volker Gruhn, Clemens Schäfer
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 11 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...