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MTV
2003
IEEE
109views Hardware» more  MTV 2003»
16 years 1 days ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
162
Voted
FAC
2008
97views more  FAC 2008»
15 years 6 months ago
A functional formalization of on chip communications
This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Julien Schmaltz, Dominique Borrione
ECBS
2007
IEEE
115views Hardware» more  ECBS 2007»
16 years 1 months ago
Modeling the Functionality of Multi-Functional Software Systems
Today, many software-based, reactive systems offer a multitude of functionality. One way to master the development of such a system is to model its functionality on an abstract le...
Alexander Gruler, Alexander Harhurin, Judith Hartm...
DAC
1999
ACM
15 years 11 months ago
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar...
FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 11 months ago
Area estimation and optimisation of FPGA routing fabrics
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for explor...
Alastair M. Smith, George A. Constantinides, Peter...