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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
16 years 5 hour ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
HICSS
2000
IEEE
138views Biometrics» more  HICSS 2000»
15 years 11 months ago
The NZDIS Project: An Agent-based Distributed Information Systems Architecture
This paper describes an architecture for building distributed information systems from existing information resources, based on software agent and distributed object technologies....
Martin K. Purvis, Stephen Cranefield, Geoff Bush, ...
205
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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 11 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
FPGA
1999
ACM
155views FPGA» more  FPGA 1999»
15 years 11 months ago
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
Vaughn Betz, Jonathan Rose
AOSD
2007
ACM
15 years 10 months ago
A flexible architecture for pointcut-advice language implementations
Current implementations for aspect-oriented programming languages map the aspect-oriented concepts of source programs to object-oriented bytecode. This hinders execution environme...
Christoph Bockisch, Mira Mezini