Sciweavers

2779 search results - page 184 / 556
» Modelling Immunological Memory
Sort
View
CVPR
2011
IEEE
15 years 2 months ago
Simulating Human Saccadic Scanpaths on Natural Images
Human saccade is a dynamic process of information pursuit. Based on the principle of information maximization, we propose a computational model to simulate human saccadic scanpath...
Wei Wang, Cheng Chen, Yizhou Wang, Tingting Jiang,...
PATMOS
2000
Springer
15 years 10 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
IEEEPACT
2002
IEEE
15 years 11 months ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
CODES
2000
IEEE
15 years 11 months ago
Frequency interleaving as a codesign scheduling paradigm
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
DDECS
2009
IEEE
149views Hardware» more  DDECS 2009»
15 years 10 months ago
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
Yiorgos Sfikas, Yiorgos Tsiatouhas