Abstract. The shared-cache contention on Chip Multiprocessors causes performance degradation to applications and hurts system fairness. Many previously proposed solutions schedule ...
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary mo...
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwa...
—Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-sp...
In this paper, we propose the first wire density driven global routing that considers CMP variation and timing. To enable CMP awareness during global routing, we propose a compac...
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Cha...