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CODES
2006
IEEE
16 years 25 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
CODES
2003
IEEE
16 years 2 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
218
Voted
ICEIS
2000
IEEE
15 years 11 months ago
Architectural Considerations with Distributed Computing
We understand distributed systems as a collection of distributed computation resources that work together as one harmonious system. It is the great achievement of computer network...
Yibing Wang, Robert M. Hyatt, Barrett R. Bryant
ICSOC
2004
Springer
16 years 4 days ago
A service-oriented architecture for digital libraries
CiteSeer is currently a very large source of meta-data information on the World Wide Web (WWW). This meta-data is the key material for the Semantic Web. Still, CiteSeer is not yet...
Yves Petinot, C. Lee Giles, Vivek Bhatnagar, Prade...
CAISE
2004
Springer
16 years 5 days ago
Object-Process Methodology (OPM) vs. UML - a Code Generation Perspective
Modeling languages have been evolving at a high pace, encouraging the use of automatic code generators for transforming models to programs. Automatic code generators should enable ...
Iris Reinhartz-Berger, Dov Dori