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DATE
2002
IEEE
108views Hardware» more  DATE 2002»
15 years 11 months ago
Networks on Silicon: Combining Best-Effort and Guaranteed Services
We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a prot...
Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeter...
AMAST
2008
Springer
15 years 8 months ago
The Verification of the On-Chip COMA Cache Coherence Protocol
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
Thuy Duong Vu, Li Zhang, Chris R. Jesshope
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 7 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
CASCON
1997
98views Education» more  CASCON 1997»
15 years 8 months ago
Similarity-based retrieval for diverse bookshelf software repository users
The paper presents a similarity-based retrieval framework for a software repository that aids the process of maintaining, understanding, and migrating legacy software systems [12]...
Igor Jurisica
EUROSYS
2007
ACM
16 years 4 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek