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» Modeling and evaluation of hardware software designs
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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 23 days ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
EMSOFT
2004
Springer
15 years 11 months ago
Loose synchronization of event-triggered networks for distribution of synchronous programs
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
Jan Romberg, Andreas Bauer 0002
ECBS
2006
IEEE
203views Hardware» more  ECBS 2006»
15 years 10 months ago
The Feature-Architecture Mapping (FArM) Method for Feature-Oriented Development of Software Product Lines
Software product lines (PLs) are large, complex systems, demanding high maintainability and enhanced flexibility. Nonetheless, in the state of the art PL methods, features are sca...
Periklis Sochos, Matthias Riebisch, Ilka Philippow
GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
16 years 21 days ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
LCPC
2005
Springer
15 years 12 months ago
Software Thread Level Speculation for the Java Language and Virtual Machine Environment
Thread level speculation (TLS) has shown great promise as a strategy for fine to medium grain automatic parallelisation, and in a hardware context techniques to ensure correct TLS...
Christopher J. F. Pickett, Clark Verbrugge