1617 search results - page 78 / 324 » Modeling and evaluation of hardware software designs |
151
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DAC
2011
ACM
14 years 6 months ago
2011
ACM
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However,...
195
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ISSS
2000
IEEE
15 years 10 months ago
2000
IEEE
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
207
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ISSS
1996
IEEE
15 years 10 months ago
1996
IEEE
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
160
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
132
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ECBS
2007
IEEE
16 years 19 days ago
2007
IEEE
Most existing work on t-way testing has focused on 2-way (or pairwise) testing, which aims to detect faults caused by interactions between any two parameters. However, faults can ...