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» Modeling and evaluation of hardware software designs
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CODES
2003
IEEE
15 years 11 months ago
A low power scheduler using game theory
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
N. Ranganathan, Ashok K. Murugavel
COMPUTER
2002
129views more  COMPUTER 2002»
15 years 6 months ago
Networks on Chips: A New SoC Paradigm
of abstraction and coarse granularity and distributed communication control. Focusing on using probabilistic metrics such as average values or variance to quantify design objective...
Luca Benini, Giovanni De Micheli
DFT
2008
IEEE
138views VLSI» more  DFT 2008»
16 years 27 days ago
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
It is widely recognized that device and interconnect fabrics at the nanoscale will be characterized by an increased susceptibility to transient faults. This appears to be intrinsi...
Andrey V. Zykov, Gustavo de Veciana
DSOM
2007
Springer
15 years 10 months ago
Bottleneck Detection Using Statistical Intervention Analysis
Abstract. The complexity of today's large-scale enterprise applications demands system administrators to monitor enormous amounts of metrics, and reconfigure their hardware as...
Simon Malkowski, Markus Hedwig, Jason Parekh, Calt...
HPDC
2008
IEEE
15 years 6 months ago
A two-level scheduler to dynamically schedule a stream of batch jobs in large-scale grids
This paper describes the study conducted to design and evaluate a two-level on-line scheduler to dynamically schedule a stream of sequential and multi-threaded batch jobs on large...
Marco Pasquali, Ranieri Baraglia, Gabriele Capanni...