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» Modeling and evaluation of hardware software designs
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ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
15 years 10 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
JSS
2006
104views more  JSS 2006»
15 years 6 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
15 years 4 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
ICGA
1997
122views Optimization» more  ICGA 1997»
15 years 7 months ago
A Comparison of Global and Local Search Methods in Drug Docking
Molecular docking software makes computational predictions of the interaction of molecules. This can be useful, for example, in evaluating the binding of candidate drug molecules ...
Christopher D. Rosin, R. Scott Halliday, William E...
HPCA
2006
IEEE
16 years 6 months ago
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors
Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulato...
David A. Penry, Daniel Fay, David Hodgdon, Ryan We...