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» Modeling and evaluation of hardware software designs
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CODES
2008
IEEE
16 years 29 days ago
You can catch more bugs with transaction level honey
In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to...
Miron Abramovici, Kees Goossens, Bart Vermeulen, J...
UIST
2010
ACM
15 years 4 months ago
Designing adaptive feedback for improving data entry accuracy
Data quality is critical for many information-intensive applications. One of the best opportunities to improve data quality is during entry. USHER provides a theoretical, data-dri...
Kuang Chen, Joseph M. Hellerstein, Tapan S. Parikh
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 10 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
FPGA
2006
ACM
139views FPGA» more  FPGA 2006»
15 years 10 months ago
Fast and accurate resource estimation of automatically generated custom DFT IP cores
This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator all...
Peter A. Milder, Mohammad Ahmad, James C. Hoe, Mar...
SAC
2008
ACM
15 years 6 months ago
UML-based design test generation
In this paper we investigate and propose a fully automated technique to perform conformance checking of Java implementations against UML class diagrams. In our approach, we reused...
Waldemar Pires, João Brunet, Franklin Ramal...