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» Modeling and evaluation of hardware software designs
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CODES
2006
IEEE
16 years 15 days ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
15 years 11 months ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
16 years 8 hour ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
MICRO
2007
IEEE
167views Hardware» more  MICRO 2007»
16 years 22 days ago
Informed Microarchitecture Design Space Exploration Using Workload Dynamics
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
Chang-Burm Cho, Wangyuan Zhang, Tao Li
MOMPES
2009
IEEE
16 years 1 months ago
ArcheOpterix: An extendable tool for architecture optimization of AADL models
For embedded systems quality requirements are equally if not even more important than functional requirements. The foundation for the fulfillment of these quality requirements ha...
Aldeida Aleti, Stefan Björnander, Lars Grunsk...