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ICC
2009
IEEE
117views Communications» more  ICC 2009»
16 years 1 months ago
Reduced-Rank Adaptive Least Bit Error-Rate Detection in Hybrid Direct-Sequence Time-Hopping Ultrawide Bandwidth Systems
— In this paper we consider the low-complexity detection in hybrid direct-sequence time-hopping ultrawide bandwidth (DS-TH UWB) systems. A reduced-rank adaptive LBER detector is ...
Qasim Zeeshan Ahmed, Lie-Liang Yang, Sheng Chen
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
16 years 1 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman
LCN
2005
IEEE
16 years 21 days ago
Performance Analysis of Multi-Fiber Synchronous Photonic Share-per-link Packet Switches
A performance model is presented for an optical packet switch architecture in which the wavelength converters are shared per output link and each output link consists of multiple ...
Ayman G. Fayoumi, Fahad A. Al-Zahrani, Abdulgader ...
HPCC
2009
Springer
15 years 11 months ago
On the Performance of Commit-Time-Locking Based Software Transactional Memory
Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing res...
Zhengyu He, Bo Hong
ISCA
2000
IEEE
81views Hardware» more  ISCA 2000»
15 years 11 months ago
Clock rate versus IPC: the end of the road for conventional microarchitectures
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with tech...
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckle...
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