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CODES
2008
IEEE
16 years 28 days ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
ISPASS
2008
IEEE
16 years 26 days ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
ISPASS
2008
IEEE
16 years 26 days ago
Configurational Workload Characterization
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
Hashem Hashemi Najaf-abadi, Eric Rotenberg
NOCS
2008
IEEE
16 years 26 days ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani
SCAM
2008
IEEE
16 years 25 days ago
Modular Decompilation of Low-Level Code by Partial Evaluation
Decompiling low-level code to a high-level intermediate representation facilitates the development of analyzers, model checkers, etc. which reason about properties of the low-leve...
Miguel Gómez-Zamalloa, Elvira Albert, Germ&...
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