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CODES
1999
IEEE
15 years 11 months ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS
- It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and the...
Woo-Chul Jeun, Soonhoi Ha
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 10 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
EUROGP
2006
Springer
112views Optimization» more  EUROGP 2006»
15 years 10 months ago
The Halting Probability in Von Neumann Architectures
Abstract. Theoretical models of Turing complete linear genetic programming (GP) programs suggest the fraction of halting programs is vanishingly small. Convergence results proved f...
William B. Langdon, Riccardo Poli
VMV
2000
146views Visualization» more  VMV 2000»
15 years 8 months ago
Efficient Importance Sampling Techniques for the Photon Map
In global illumination computations the photon map is a powerful tool for approximating the irradiance, which is stored independent from scene geometry. By presenting a new algori...
Alexander Keller, Ingo Wald