2805 search results - page 302 / 561 » Modeling Memory for Melodies |
188
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SAC
2009
ACM
16 years 1 months ago
2009
ACM
Parallel architectures are the way of the future, but are notoriously difficult to program. In addition to the low-level constructs they often present (e.g., locks, DMA, and non-...
177
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SP
2009
IEEE
16 years 1 months ago
2009
IEEE
We present a logic for reasoning about properties of secure systems. The logic is built around a concurrent programming language with constructs for modeling machines with shared ...
143
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ICPR
2008
IEEE
16 years 1 months ago
2008
IEEE
The conventional octree construction method is implemented iteratively at consecutive subdivision levels. The resultant octree models at different subdivision levels contain quite...
170
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MEMOCODE
2008
IEEE
16 years 1 months ago
2008
IEEE
—Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system’...
174
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...