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ICALP
2007
Springer
16 years 21 days ago
Checking and Spot-Checking the Correctness of Priority Queues
We revisit the problem of memory checking considered by Blum et al. [3]. In this model, a checker monitors the behavior of a data structure residing in unreliable memory given an a...
Matthew Chu, Sampath Kannan, Andrew McGregor
PDP
2005
IEEE
16 years 3 days ago
A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol
SVM systems are a cheaper and flexible way to implement the shared memory programming paradigm. Their huge flexibility is due to their software implementation; however, this is al...
Salvador Petit, Julio Sahuquillo, Ana Pont
IPPS
2000
IEEE
15 years 11 months ago
Predicting Performance on SMPs. A Case Study: The SGI Power Challenge
We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andre...
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
15 years 11 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ASPLOS
2000
ACM
15 years 11 months ago
Power Aware Page Allocation
One of the major challenges of post-PC computing is the need to reduce energy consumption, thereby extending the lifetime of the batteries that power these mobile devices. Memory ...
Alvin R. Lebeck, Xiaobo Fan, Heng Zeng, Carla Schl...