356 search results - page 27 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
151
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
- It is attractive to use the OpenMP as a parallel programming model on a Multiprocessor System-On-Chip (MPSoC) because it is easy to write a parallel program in the OpenMP and the...
166
Voted
ASPDAC
2009
ACM
15 years 3 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
155
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
176
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PACT
2007
Springer
16 years 1 days ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
166
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ICPP
1991
IEEE
15 years 9 months ago
1991
IEEE
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...