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FPL
2003
Springer
81views Hardware» more  FPL 2003»
16 years 41 min ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
IJHR
2008
117views more  IJHR 2008»
15 years 6 months ago
Implementation of Cognitive Control for a Humanoid Robot
Engineers have long used control systems utilizing models and feedback loops to control realworld systems. Limitations of model-based control led to a generation of intelligent co...
Kazuhiko Kawamura, Stephen M. Gordon, Palis Ratana...
ANCS
2009
ACM
15 years 4 months ago
A NFA-based programmable regular expression match engine
Pattern matching is the most computation intensive task of a network intrusion detection system (NIDS). In this paper we present a hardware architecture to speed up the pattern mat...
Derek Pao
151
Voted
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
16 years 1 months ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk
ISQED
2009
IEEE
136views Hardware» more  ISQED 2009»
16 years 1 months ago
NBTI aware workload balancing in multi-core systems
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet ...