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CODES
2006
IEEE
15 years 10 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
GECCO
2006
Springer
155views Optimization» more  GECCO 2006»
15 years 10 months ago
Comparison of genetic representation schemes for scheduling soft real-time parallel applications
This paper presents a hybrid technique that combines List Scheduling (LS) with Genetic Algorithms (GA) for constructing non-preemptive schedules for soft real-time parallel applic...
Yoginder S. Dandass, Amit C. Bugde
CASES
2001
ACM
15 years 10 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic
ITC
1991
IEEE
80views Hardware» more  ITC 1991»
15 years 10 months ago
An Intelligent Approach to Automatic Test Equipment
In diagnosing a failed system, a smart technician would choose tests to be performed based on the context of the situation. Currently, test program sets do not fault-. isolate wit...
William R. Simpson, John W. Sheppard
ASAP
2008
IEEE
120views Hardware» more  ASAP 2008»
15 years 8 months ago
Lightweight DMA management mechanisms for multiprocessors on FPGA
This paper presents a multiprocessor system on FPGA that adopts Direct Memory Access (DMA) mechanisms to move data between the external memory and the local memory of each process...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...