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ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
16 years 3 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
SENSYS
2009
ACM
16 years 1 months ago
Macrodebugging: global views of distributed program execution
Creating and debugging programs for wireless embedded networks (WENs) is notoriously difficult. Macroprogramming is an emerging technology that aims to address this by providing ...
Tamim I. Sookoor, Timothy W. Hnat, Pieter Hooimeij...
CCS
2009
ACM
16 years 1 months ago
A new cell counter based attack against tor
Various low-latency anonymous communication systems such as Tor and Anoymizer have been designed to provide anonymity service for users. In order to hide the communication of user...
Zhen Ling, Junzhou Luo, Wei Yu, Xinwen Fu, Dong Xu...
CASES
2009
ACM
16 years 1 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
16 years 1 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...