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ICCAD
1996
IEEE
119views Hardware» more  ICCAD 1996»
15 years 11 months ago
An algorithm for synthesis of system-level interface circuits
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...
Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
ISSS
1996
IEEE
125views Hardware» more  ISSS 1996»
15 years 11 months ago
Size-Constrained Code Placement for Cache Miss Rate Reduction
In design of an embedded system with a cache, it is important to minimize the cache miss rate to reduce the power consumption as well as to improvethe performance of the system. W...
Hiroyuki Tomiyama, Hiroto Yasuura
CODES
2004
IEEE
15 years 10 months ago
Power-aware communication optimization for networks-on-chips with voltage scalable links
Networks-on-Chip (NoC) is emerging as a practical development platform for future systems-on-chip products. We propose an energyefficient static algorithm which optimizes the ener...
Dongkun Shin, Jihong Kim
ANCS
2008
ACM
15 years 8 months ago
Design of a scalable network programming framework
Nearly all programmable commercial hardware solutions offered for high-speed networking systems are capable of meeting the performance and flexibility requirements of equipment ve...
Ben Wun, Patrick Crowley, Arun Raghunath
CASES
2005
ACM
15 years 8 months ago
Intra-task scenario-aware voltage scheduling
Modern embedded applications usually have real-time constraints and they have requirements for low energy consumption. At system level, intra-task dynamic voltage scaling (DVS) is...
Stefan Valentin Gheorghita, Twan Basten, Henk Corp...