The contribution of this paper is threefold. First, an improvement to a previously published paper on the timing analysis of Controller Area Network (CAN) in the presence of trans...
This paper targets energy-efficient scheduling of tasks over multiple processors, where tasks share a common deadline. Distinct from many research results on heuristics-based ener...
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
—Real-time applications typically operate under strict timing and dependability constraints. Although traditional data replication protocols provide fault tolerance, real-time gu...
Ashish Mehra, Jennifer Rexford, Hock-Siong Ang, Fa...
We propose an approach for timing analysis of software-based embedded computer systems that builds on the established probabilistic framework of Bayesian networks. We envision an ...