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ECRTS
2008
IEEE
16 years 1 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
ECRTS
2008
IEEE
16 years 1 months ago
A Hierarchical Multiprocessor Bandwidth Reservation Scheme with Timing Guarantees
A multiprocessor scheduling scheme is presented for supporting hierarchical containers that encapsulate sporadic soft and hard real-time tasks. In this scheme, each container is a...
Hennadiy Leontyev, James H. Anderson
ECRTS
2008
IEEE
16 years 1 months ago
WCET-driven Cache-based Procedure Positioning Optimizations
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...
Paul Lokuciejewski, Heiko Falk, Peter Marwedel
ISCAS
2008
IEEE
154views Hardware» more  ISCAS 2008»
16 years 1 months ago
A 6.3nJ/op low energy 160-bit modulo-multiplier for elliptic curve cryptography processor
— A low energy modulo-multiplier is proposed for elliptic curve cryptography (ECC) processor, especially for authentication in mobile device or key encryption in embedded health-...
Hyejung Kim, Yongsang Kim, Hoi-Jun Yoo
SEUS
2008
IEEE
16 years 1 months ago
Analysis of User Perceived QoS in Ubiquitous UMTS Environments Subject to Faults
This paper provides a QoS analysis of a dynamic, ubiquitous UMTS network scenario in the automotive context identified in the ongoing EC HIDENETS project. The scenario comprises d...
Andrea Bondavalli, Paolo Lollini, Leonardo Montecc...