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VTS
2003
IEEE
119views Hardware» more  VTS 2003»
15 years 11 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
SPAA
2000
ACM
15 years 10 months ago
An experimental study of a simple, distributed edge coloring algorithm
We conduct an experimental analysis of a distributed, randomized algorithm for edge coloring graphs. The algorithm is extremely simple, yet, according to the probabilistic analysi...
Madhav V. Marathe, Alessandro Panconesi, Larry D. ...
ICCAD
1996
IEEE
144views Hardware» more  ICCAD 1996»
15 years 10 months ago
Validation coverage analysis for complex digital designs
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
Richard C. Ho, Mark Horowitz
CP
2008
Springer
15 years 8 months ago
Approximate Compilation of Constraints into Multivalued Decision Diagrams
We present an incremental refinement algorithm for approximate compilation of constraint satisfaction models into multivalued decision diagrams (MDDs). The algorithm uses a vertex ...
Tarik Hadzic, John N. Hooker, Barry O'Sullivan, Pe...