Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
We conduct an experimental analysis of a distributed, randomized algorithm for edge coloring graphs. The algorithm is extremely simple, yet, according to the probabilistic analysi...
Madhav V. Marathe, Alessandro Panconesi, Larry D. ...
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
We present an incremental refinement algorithm for approximate compilation of constraint satisfaction models into multivalued decision diagrams (MDDs). The algorithm uses a vertex ...
Tarik Hadzic, John N. Hooker, Barry O'Sullivan, Pe...