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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
16 years 3 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
FM
2009
Springer
163views Formal Methods» more  FM 2009»
15 years 11 months ago
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
Faranak Heidarian, Julien Schmaltz, Frits W. Vaand...
ISSTA
2000
ACM
15 years 11 months ago
Finding bugs with a constraint solver
A method for finding bugs in code is presented. For given small numbers j and k, the code of a procedure is translated into a relational formula whose models represent all executi...
Daniel Jackson, Mandana Vaziri
BIRTHDAY
2009
Springer
15 years 10 months ago
Modular Verification of Strongly Invasive Aspects
An extended specification for aspects, and a new verification method based on model checking are used to establish the correctness of strongly-invasive aspects, independently of a...
Emilia Katz, Shmuel Katz
HASE
2007
IEEE
15 years 10 months ago
Validation Support for Distributed Real-Time Embedded Systems in VDM++
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...