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ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
16 years 8 days ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
INEX
2005
Springer
16 years 6 days ago
A Flexible Structured-Based Representation for XML Document Mining
This paper reports on the INRIA group’s approach to XML mining while participating in the INEX XML Mining track 2005. We use a flexible representation of XML documents that allo...
Anne-Marie Vercoustre, Mounir Fegas, Saba Gul, Yve...
PATMOS
2005
Springer
16 years 6 days ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
WMPI
2004
ACM
16 years 3 days ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
EUROPAR
2004
Springer
16 years 3 days ago
Improving the Scalability of Logarithmic-Degree DHT-Based Peer-to-Peer Networks
High scalability in Peer-to-Peer (P2P) systems has been achieved with the emergence of the networks based on Distributed Hash Table (DHT). Most of the DHTs can be regarded as expon...
Bruno Carton, Valentin Mesaros