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ISPASS
2008
IEEE
16 years 1 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
ICC
2007
IEEE
301views Communications» more  ICC 2007»
16 years 1 months ago
Network Lifetime Optimization by Duality Approach for Multi-Source and Single-Sink Topology in Wireless Sensor Networks
—The multi-source and single-sink (MSSS) topology, in wireless sensor networks, is defined as the network topology, where all of nodes can gather, receive and transmit data to t...
Hui Wang, Yuhang Yang, Maode Ma, Xiaomin Wang
MICRO
2007
IEEE
184views Hardware» more  MICRO 2007»
16 years 1 months ago
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlk...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 23 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ASPLOS
2006
ACM
16 years 21 days ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
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