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QEST
2006
IEEE
16 years 18 days ago
Compositional Performability Evaluation for STATEMATE
Abstract— This paper reports on our efforts to link an industrial state-of-the-art modelling tool to academic state-of-the-art analysis algorithms. In a nutshell, we enable timed...
Eckard Böde, Marc Herbstritt, Holger Hermanns...
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 10 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt
ISOLA
2010
Springer
15 years 5 months ago
Enforcing Applicability of Real-Time Scheduling Theory Feasibility Tests with the Use of Design-Patterns
Abstract. This article deals with performance verifications of architecture models of real-time embedded systems. We focus on models verified with the real-time scheduling theory...
Alain Plantec, Frank Singhoff, Pierre Dissaux, J&e...
SIGSOFT
2007
ACM
16 years 7 months ago
Finding bugs efficiently with a SAT solver
We present an approach for checking code against rich specifications, based on existing work that consists of encoding the program in a relational logic and using a constraint sol...
Julian Dolby, Mandana Vaziri, Frank Tip
UML
2001
Springer
15 years 11 months ago
Designing Procedural 4GL Applications through UML Modeling
: This paper presents a Unified Modeling Language (UML) model for VisualAge Generator (VG) business-oriented applications. This model was defined to bridge between two different mo...
Shiri Davidson, Mila Keren, Sara Porat, Gabi Zodik