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IPPS
1998
IEEE
15 years 10 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
ICDCS
2010
IEEE
15 years 10 months ago
A New Buffer Cache Design Exploiting Both Temporal and Content Localities
: This paper presents a Least Popularly Used buffer cache algorithm to exploit both temporal locality and content locality of I/O requests. Popular data blocks are selected as refe...
Jin Ren, Qing Yang
EUROPAR
2009
Springer
15 years 10 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
HPCC
2007
Springer
15 years 10 months ago
A Highly Efficient Parallel Algorithm for H.264 Encoder Based on Macro-Block Region Partition
This paper proposes a highly efficient MBRP parallel algorithm for H.264 encoder, which is based on the analysis of data dependencies in H.264 encoder. In the algorithm, the video ...
Shuwei Sun, Dong Wang, Shuming Chen
PC
2007
173views Management» more  PC 2007»
15 years 6 months ago
Parallel graphics and visualization
Parallel volume rendering is one of the most efficient techniques to achieve real time visualization of large datasets by distributing the data and the rendering process over a c...
Luís Paulo Santos, Bruno Raffin, Alan Heiri...