21007 search results - page 3770 / 4202 » Mobile Parallel Computing |
233
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
165
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
154
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the outpu...
180
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...
159
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HPCA
2006
IEEE
16 years 7 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...